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copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor databooks. application note 52 using the dallas phantom real time clocks application note 52 022394 1/13 description the dallas phantom real time clocks are a family of devices that offer the combination of a transparent cmos timekeeper and a nonvolatile static ram meet- ing the standard jedec bytewide pinouts. some vari- eties of the dallas phantom real time clocks also pro- vide a transparent cmos timekeeper for use with rom. the timekeeper is transparent to the ram/rom memory map because it does not occupy any of the existing ram/rom locations. these devices are termed aphantomo because the timekeeper is accessed only when a predetermined 64bit pattern has been received by the device. when the timekeeper is not being accessed, the ram/rom can be accessed nor- mally. the timekeeper keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. in the absence of power, a lithium energy source maintains the timekeeping operation and retains data in the cmos static ram. family overview DS1215: the heart of the dallas phantom real time clock family is the DS1215 phantom time chip. this integrated cir- cuit is a combination of a cmos timekeeper and a non- volatile memory controller. in the absence of power, an external battery maintains the timekeeping operation and retains data in the cmos static ram. the watch keeps track of hundredths of seconds, seconds, min- utes, hours, day, date, month, and year information. the last day of the month is automatically adjusted for months with less than 31 days, including correction for leap year every four years. the real time clock operates in one of two formats: 12hour mode with an am/pm indicator or a 24hour mode . the nonvolatile controller supplies all the necessary support circuitry to convert a cmos ram to a nonvolatile memory. the DS1215 can also be used to provide timekeeping functions with rom. ds1216: stemming from the DS1215 are the ds1216 smart- watch intelligent sockets. the smartwatch is a 600 mil wide dip socket with a builtin DS1215 (providing timekeeping functions and a nonvolatile ram control- ler), an embedded lithium energy source, and a 32.768 khz crystal. when the socket is mated with a bytewide cmos static ram, it provides a complete solution to problems associated with memory volatility and uses a common energy source to maintain time and date. the ds1216 can also be mated with a rom to provide time- keeping capability only. figures 1 and 2 show the basic interface of a smartwatch with ram inserted and a smartwatch with rom inserted, respectively. ds1243y, ds1244y, ds1248y: the ds124x nonvolatile sram with phantom time clock modules are the final members of the dallas phantom real time clock family. these devices are fully nonvolatile static ram with a builtin phantom clock, embedded lithium energy source, and 32.768 khz crystal. these devices operate identical to a ds1216 with a ram inserted. the ds124x nonvolatile sram with phantom time clock modules will maintain over 10 years of data retention in the absence of power. perhaps the best way to sum up the dallas phantom real time clock family is as follows. the DS1215 phantom time chip is the basic building block that pro- vides timekeeping and a nonvolatile memory controller. the ds1216 then adds a crystal and lithium energy source to the DS1215 and encapsulates them all in a socket that will accept either a ram or a rom. finally, the ds124x modules contain both nonvolatile ram and timekeeping features in a readytouse package. the entire dallas phantom real time clock family is shown in table 1.
application note 52 022394 2/13 table 1 DS1215 phantom time chip ds1216b smartwatch/ram 16k/64k ds1216c smartwatch/ram 64k/256k ds1216d smartwatch/ram 256k/1m ds1216e smartwatch/rom 64k/256k ds1216f smartwatch/rom 64k/256k/1m ds1243y 64k nv sram with phantom clock ds1244y 256k nv sram with phantom clock ds1248y 1024k nv sram with phantom clock application the dallas phantom real time clock family offers two features that will greatly enhance a system. the first feature is nonvolatile ram capability. the second fea- ture is that the phantom clock is transparent to the ram and therefore timekeeping capacity can be added to a system without changing the existing hardware. all that is required is an existing bytewide memory socket. the retrofit capability is maximized through the transparent interfaces supported by the phantom time chip. also advantageous to the designer is that an upgrade path is provided to higher ram densities with the ds124x modules or to higher ram/rom densities with the ds1216. it should be mentioned that there is some software over- head that is associated with having timekeeping func- tions that are transparent to ram as will be discussed in detail below. if it is determined that a transparent clock is not necessary, then the ds164x nonvolatile time- keeping ram family could offer an excellent solution to your timekeeping and nonvolatile sram needs. these offer nonvolatile sram with the real time clock regis- ters located in the ram address space. another pos- sible solution are the ds1386 or ds1486 ramified watchdog timekeepers which offer nonvolatile ram and real time clock as well as a few extra features including alarm function and watchdog timer. operation nonvolatile ram operation one important feature of the dallas phantom real time clocks is that the nonvolatile ram can be used to store system configuration data and since the clock is trans- parent to the ram, no memory is lost to timekeeping needs. when the phantom clock is not accessed, the ce signal is passed on to the chip enable of the memory. reading and writing to the ram is identical to that of a standard ram chip. figure 1 illustrates a typical ram/ time chip interface. note that this is the basic interface used for the ds1216 smartwatch/ram and the ds124x. the phantom real time clock family performs circuit functions required to make a cmos ram nonvolatile. first, a switch is provided to direct power from the bat- tery or v cc supply depending on which is greater. the second function provided is powerfail detection. power fail detection occurs when v cci falls below v tp , which is equal to 1.26 x v bat . when v cci goes out of tolerance, a comparator outputs a powerfail signal to the chip enable logic. the third function accomplishes write protection by holding the chip enable signal to the memory (ceo ) within 0.2 volts of v cc or battery as long as v cc is out of tolerance. during nominal power supply conditions the memory chip enable signal (ceo ) will track the chip enable signal (cei ) sent to the socket with a maximum propagation delay of 20 ns. finally, an important consideration when using the ds1216 is to select a ram that draws no more than a maximum of 1 m a. if the ram data retention current is larger than 1 m a, the device will not meet the data reten- tion expectations of more than 10 years at 25 c. in the 10 year data retention calculation for the ds1216, it is assumed that system power will be on 20% of the time. perhaps the best way to insure that a data retention of 10 years at 25 c is met is to use one of the ds124x modules with selfcontained nonvolatile ram. the ds124x modules will insure data retention for 10 years regardless of how often the system power is on. rom operation the DS1215 and ds1216(e/f) can also be used in con- junction with a rom. a typical rom/time chip inter- face is illustrated in figure 2. in this configuration, the rom/ram pin is connected to v cco to select the rom mode of operation. since rom is a readonly device that retains data in the absence of power, battery backup and write protection is not required. as a
application note 52 022394 3/13 result, the chip enable logic will force ceo low when power fails. the real time clock does retain the same internal nonvolatility and write protection as described in the ram mode. real time clock operation the block diagram of figure 3 illustrates the main ele- ments of the phantom clock. communication with the phantom clock is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper write data as shown in figure 4. all accesses which occur prior to recognition of the 64bit pattern are directed to memory via the chip enable output pin (ceo ). after recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock and ceo remains high during this time, disabling the connected memory. data transfer to and from the phantom clock is accom- plished with a serial bit stream under the control of chip enable input (cei ), output enable (oe ), and write enable (we ). initially, a read cycle using the cei and oe control of the phantom clock starts the pattern recogni- tion sequence by moving a pointer to the first bit of the 64bit comparison register. next, 64 consecutive write cycles are executed using the cei and we control of the phantom clock. these 64 write cycles are used only to gain access to the phantom clock. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a scratch pad for the phantom clock. when the first write cycle is executed, it is compared to bit 0 of the 64bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored until a read cycle is encountered which resets the comparison register pointer to the beginning of the 64bit comparison reg- ister. if a read cycle occurs at any time during the pat- tern recognition process, the present sequence is aborted and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all the bits in the com- parison register have been matched (this bit pattern is shown in figure 4). with a correct match of the 64 bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to either receive or transmit data, depending on the level of the oe pin or the we pin. data will either be written to or read from the eight phantom clock registers shown in figure 5. cycles to other locations outside the memory block can be interleaved with ce cycles without inter- rupting the pattern recognition sequence or data trans- fer sequence to the phantom clock. figure 6 offers an example of pseudo code for both accessing the phantom clock embedded in a ram through pattern recognition and interfacing with the clock registers. another source code example is given in figure 7. this code is used for interfacing with the 8051 microcontroller. also, refer to the data book for timing diagrams for both read and write cycles. interfacing the phantom time clock with a rom is somewhat different from that of a ram. this is due to the fact that no writes are made to a rom. since there are no we or data in signals associated with the rom, the phantom time clock instead uses two address lines to access the real time clock as can be seen in figure 2. in summary, the operation of the phantom clocks is best defined as operating in two different modes. the first being the pattern match mode. in this mode, the phantom clock is transparent to the system yet moni- tors communication to the ram waiting for a match of it's 64bit access pattern. when the 64bit access pat- tern has been written, the phantom clocks enter the clock access mode. in this mode, the eight phantom clock registers are available to be written or read and will stay in this mode until all eight registers have been accessed, until a reset has been executed, or until a power fail. troubleshooting the dallas phantom real time clocks have proven to be highly reliable and meet the published specifications. however, in the course of development, several com- mon difficulties could be experienced. to reduce these difficulties, dallas semiconductor has gathered the common difficulties and pitfalls into a troubleshooting guide to assist users.
application note 52 022394 4/13 common difficulties cannot access clock registers several items can cause this phenomena. 1. comparison register pointer has has not been set to the first bit . the phantom real time clock hides behind the sram and waits for a match to it's 64bit access pattern. in this mode (the pattern match mode), every write operation to the ram will be interpreted as an attempt to match the access pat- tern by matching the value written to dq0 (d for the DS1215) to the pattern bit pointed to by the pattern match pointer. it is possible that a partial match of the pattern can occur during normal operation of a system. it is best to assume that there is a partial match of the access pattern and that the comparison register pointer is not pointing to the first bit of the match pattern. therefore, the comparison register pointer must be reset to the first pattern bit before writing the match pattern. this is accomplished by performing one read operation of the ram before writing the match pattern. 2. device is in clock access mode after system reset or interrupt . it is possible that during the course of pre- vious operation, the phantom clock had been accessed, but had not gone back into pattern match mode before a system reset or interrupt occurred. in other words, data bits would be written to or read from the phantom clock registers rather than the ram. a solution to this problem is to execute 65 consecutive read cycles immediately after an inter- rupt or system reset. this will insure that the device is taken out of the clock access mode (by reading a maximum of 64 bits) and will reset the comparison register pointer. 3. access pattern has been input in reverse order . insure that the pattern is input in the following order. start with bit 0 of byte 0 continuing to bit 7 of byte 7. 4. device is being reset . insure that the device is not accidentally being reset. this can especially be a problem with the ds1216c, ds1216d, and ds1244y where the reset pin is shared with an address pin. in this situation, that particular address line must never be taken low unless the reset bit (byte 4, bit 4) of the phantom clock is disabled, otherwise the device will be reset and the data trans- fer will be aborted. 5. device is in constant write protect mode . if only one battery is being used for the DS1215, ensure that the bat2 pin is grounded. if this pin remains floating it is possible that the device will think that a power fail condition has occurred. this is due to the method in which power fail is detected. a power fail is deter- mined to have occurred when v cc is less than v tp , which is equal to 1.26 x v bat . if v bat2 is floating, it is possible that the node could float to a value such that v tp is equal to v cc and thus the device will always be in a write protect mode. device will not oscillate 1. oscillator enable bit is disabled . insure that the oscillator enable bit (bit 5 of byte 4) is at logic 0. 2. wrong crystal used (DS1215) . insure that the cor- rect crystal is being used. it is very important that a crystal with a load capacitance of 6 pf is used. dal- las semiconductor recommends seiko part number dsvt200, daiwa part number dt26s, or equiv- alent. 3. poor crystal connection (DS1215) . to insure the greatest performance, insure that the crystal is placed as close as possible to the crystal input pins. it should also be mentioned that the DS1215 does not require load capacitors or feedback resistors. note: it should also be mentioned that it is difficult to determine if the device is oscillating by trying to mea- sure the frequency with an oscilloscope probe. this is because of the loading caused by the scope probe which can kill the oscillator. timekeeping inaccurate 1. input pins driven higher than v cc . it is very impor- tant to insure that input pins never go above v cc . if any input is allowed to go above v cc , it is possible that the oscillator may be briefly stopped which will cause the device to lose time. 2. wrong crystal used (DS1215) . for best accuracy, insure that the correct crystal is used.
application note 52 022394 5/13 ram is losing data when powered down. this problem can occur especially in nmos processors which become unstable at a higher voltage than cmos processors. this problem manifests itself in the method in which power fail is determined. write protection is asserted when v cc drops below v tp , which is equal to 1.26 x v bat . typically, the battery has a voltage of ~3.0v which leads to a v tp of 3.78v. therefore, in a power down situation, if the processor becomes unstable at a v cc of greater than ~3.78v (which is often the case for an nmos processor), a spurious write cycle could cor- rupt the data in the phantom clock. the solution to this problem is to ensure that the processor is reset before it becomes unstable and thus prevent any unwanted writes from being executed. this can be accomplished by monitoring v cc by one of dallas semiconductor's power monitors (the ds123x family) which generate a reset signal when v cc is out of tolerance. can not read consecutive hundredths of seconds. it is not possible to read consecutive hundredths of seconds because the access time to read the clock reg- isters is too long. common pitfalls device needs separate read and write signals . the dal- las phantom real time clocks were designed with intel timing in mind. therefore it is necessary to have sepa- rate read and write signals. it should be further stressed that simply complementing one signal to arrive at the other is not sufficient because this will cause the pattern match pointer to be reset during each write cycle since the oe signal will toggle whenever the we signal toggles. battery attachment (DS1215) . any battery attached to the bat1 or bat2 pins must be connected directly to the pin. it should be noted that a diode should not be con- nected between the battery input pin and the battery. this is not necessary because internal reverse charging current protection circuitry is provided and is ul recog- nized (#e99151). rom/ ram pin (DS1215) . insure that the rom/ram pin is set to the correct value. reading and writing to clock registers . it is important that all 64 bits be read or written to when the clock regis- ters have been accessed. if this is not done, the device will remain in the clock access mode. do not water wash ds1216 intelligent sockets . water washing for flux removal must not be performed on the ds1216 intelligent sockets because contaminants in the water can cause discharging of the internal lithium energy source. crystal selection (DS1215) . a 32.768 khz quartz crys- tal, seiko part number dsvt200, daiwa part number dt26s, or equivalent should be used. the crystal selected for use must have a specified load capacitance of 6 pf. the use of an incorrect crystal can kill the oscil- lator or cause accuracy problems. also, the use of an external trim capacitor to adjust the oscillator is discour- aged. it is recommended that one of the dallas smartwatch or nonvolatile sram with phantom time clock devices be selected for the highest accuracy ( 1 minute/month).
application note 52 022394 6/13 ram/time chip interface figure 1 cmos static ram add data i/o we oe ce DS1215 ceo oe we cei rst bat 1 x 1 bat 2 x 2 v cco d q v cci rom/ ram + + bat 1 bat 2 12 32.768 khz 414 13 11 3 12 10 9 7 6 15 +5 vdc a0 an dq0dq7 ce rst or tie to gnd for one-battery operation v cc we oe 16 rom/time chip interface figure 2 rom add data out a2 oe a0 DS1215 d oe we cei rst bat 1 x 1 bat 2 x 2 ceo q v cci v cco rom/ ram + + bat 1 bat 2 12 32.768 khz 414 13 11 3 12 6 9 16 7 10 +5 vdc a0 an d0 d7 ce rst or tie to gnd for one-battery operation ce v cc oe 15
application note 52 022394 7/13 timing block diagram figure 3 clock/calendar logic update timekeeping register comparison register internal v cc v cco v cci x 1 x 2 d q data power-fail write read ceo rom/ram bat 1 bat 2 32.768 khz cei oe we rst control logic access enable sequence detector i/o buffers powerfail detect logic
application note 52 022394 8/13 time chip comparison register definition figure 4 76543210 11000101 00111010 10100011 01011100 11000101 00111010 10100011 01011100 c5 3a a3 5c c5 3a a3 5c byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 hex value note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent entry to the time chip are less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb.
application note 52 022394 9/13 time chip register definition figure 5 7654 3210 0.1 sec 0099 0059 0059 0112 0107 0131 0112 0099 0 1 2 3 4 5 6 7 range (bcd) register 0 0 12/24 0 10 hr 00 0 00 0 0 0 10 month 10 year year 0.01 sec 0023 10 sec seconds 10 min minutes a/p hour osc rst day 10 date date month
application note 52 022394 10/13 pseudo code figure 6 * this code will access the phantom time clock by sending the 64bit * * access pattern. then the time data will be written to the clock and * * finally the phantom time clock will be accessed again and it will be * * read. the time information to be written is 12:00 pm wednesday, * * january 1, 1992. also note that the oscillator has been enabled and * * reset has been disabled. * a : array[0..7] = (c5, 3a, a3, 5c, c5, 3a, a3, 5c) (access pattern) t : array[0..7] = (00, 00, 00, b2, 14, 01, 01, 92) (time data) x : byte at 1000 (memory location 1000h) d : array [0..7] s : byte * send access pattern to phantom time clock * for i = 0 to 64 s = x (perform 65 consecutive reads from x) for i = 0 to 7 (loop for 8 bytes) for j = 0 to 7 (loop for 8 bits) x = a[i] shr j (write to x, shift bits right j) next j next i * write time data to phantom time clock registers * for i = 0 to 7 (loop for 8 bytes) for j = 0 to 7 (loop for 8 bits) x = t[i] shr j (write to x, shift bits right j) next j * send access pattern to phantom time clock * for i = 0 to 64 s = x (perform 65 consecutive reads from x) for i = 0 to 7 (loop for 8 bytes) for j = 0 to 7 (loop for 8 bits) x = a[i] shr j next j next i * read phantom time clock registers * for i = 0 to 7 (loop for 8 bytes) d[i] = 0 (initiate the byte) for j = 0 to 7 (loop for 8 bits) d[i] = d[i] or (x and 1) shl j (position bits in byte) next j next i
application note 52 022394 11/13 example source code for 8051 microcontroller figure 7 ; 8051code.doc ; rtc procedure to access the DS1215 serial timekeeper, or ds1216 ; smartwatch using 8031, 8051 or 80c196 ; bit_seg segment bit rseg bitseg wf: dbit 1 byte_seg segment data rseg byte_seg buff: ds 8 ;centisec: 0099 ; ;seconds: 0059 ; ;minutes: 0059 ; ;hours: 0112 / 0023 ; ;day:1nhex % rst off, n=day# 0107 ; ;date: 0131 ; ;month: 0112 ; ;year: 0099 codeseg segment code rseg code_seg ;************************** ;*** main program goes here ;************************** ; ; main program sets wf for read mode and on return from rtc the buff will ; contain the 8 bytes of data read from the clock. if wf is cleared then ; rtc will return after writing the 8 byte buff to the clock. ; ; note !!! : refer to the DS1215 (ram mode) or ds1216 data sheet. ; rtc: push psw ;save user registers. push acc push b mov b, ro push b mov ro, #buff ;load pointer to start of table. lcall open ;set up to open the ds1216. mov b, #8h ;load loop counter for 8 bytes. jnb wf, writetime ;read/write mode check. ; readtime: lcall rbyte ;read one byte. mov @ro, a ;save in rtn temporary register. inc r0 ;temporary data register pointer. djnz b, readtime ;loop to read 8 bytes. sjmp endtime ;done reading goto finish. ; writetime: mov a, @r0 ;load byte of data to be written. lcall wbyte ;write one byte. inc r0 ;temporary data register pointer. djnz b, writetime ;loop to write 8 bytes.
application note 52 022394 12/13 ; endtime: pop b ;restore registers. mov r0, b pop b pop acc pop psw ret ;return to main calling program. ; ; ; ; ;************************************** ; subroutine to open the clock/calendar ;************************************** ; ; this subroutine executes the sequence of reads and writes which ; is required in order to open communication with the timekeeper. ; open: lcall close ;make sure it is closed. mov b, #4 ;set pattern period count. mov a, #0c5h ;load first byte of pattern. opena: lcall wbyte ;send out the byte. xrl a, #0ffh ;generate next pattern byte. lcall wbyte ;send out the byte. swap a ;generate next pattern byte. djnz b, opena ;repeat until 8 bytes sent. ret ;return. ; ;****************************** ;*** subroutine to close clock ;****************************** ; ; this subroutine insures that the registers of the timekeeper ; are closed by executing 72 successive reads of the date and time ; registers. ; close: mov b, #9 ;set up to read 9 bytes. closea: lcall rbyte ;read a byte. djnz b, closea ;loop for 9 byte reads. ret ;return ; ;*********************************** :*** subroutine to read a data byte ;*********************************** ; rbyte: push dpl ;save the data push dph ; pointer on stack. push b ;save the b register. mov dptr, #rtcaddr ;enable the clock. mov b, #8 ;set the bit count.
application note 52 022394 13/13 li: push acc ;save the accumulator. movx a, @dptr ;input the data bit. rrc a ;move it to carry. pop acc ;get the accumulator. rrc a ;save the data bit. djnz b, li ;loop for a whole byte. pop b ;restore the b register. pop dph ;restore the data pop dpl ; pointer from stack. ret ;return. ; ; ; ;*********************************** ;*** subroutine to write a data byte ;*********************************** ; wbyte: push dpl ;save the data push dph ; pointer on stack. push b ;save the b register. mov dptr, #rtcaddr ;enable the clock. mov b, #8 ;set the bit count. lo: push acc ;save the accumulator. anl a, #1 ;set up bit for output. movx @dptr, a ;output the data bit. pop acc ;restore the accumulator. rr a ;position next bit. djnz b, lo ;loop for a whole byte. pop b ;restore the b register. pop dph ;restore the data pop dpl ; pointer from stack. ret ;return. ; ;*************** ;end of program ;*************** ; end ;end of program.

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